The JM467D643A-60 is a 64M x 64bits Double Data Rate SDRAM high-density for DDR333. The JM467D643A-60 consists of 8pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP-II 400mil packages, and a 2048 bits serial EEPROM on a 200-pin printed circuit board. The JM467D643A-60 is a Dual In-Line Memory Module and is intended for mounting into 200-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features
- Power supply: VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V
- Max clock Freq: 166MHZ.
- Double-data-rate architecture; two data transfers per clock cycle
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transition with CK transition
- Auto and Self Refresh 7.8us refresh interval.
- Data I/O transactions on both edge of data strobe.
- Edge aligned data output, center aligned data input.
- Serial Presence Detect (SPD) with serial EEPROM
- SSTL-2 compatible inputs and outputs.
- MRS cycle with address key programs. CAS Latency (Access from column address) : 2.5 Burst Length (2,4,8 ) Data Sequence (Sequential & Interleave)
In range since: 27.10.2004